In recent years, with the trend of scaling down the size of MIS transistors constituting a semiconductor integrated circuit, the thickness of a gate insulating film made of silicon oxide has been rapidly reduced. However, when the thickness of the gate insulating film is reduced to about 2 nm, a gate-leakage phenomenon in which electrons in a silicon substrate pass through a gate insulating film to escape to a gate electrode becomes conspicuous due to the quantum effect called direct tunneling.
Therefore, studies on the replacement of a gate insulating film material to a high dielectric material whose relative dielectric constant is higher than that of silicon oxide (SiO2) have been proceeding. This is because, when a high dielectric film is used to form a gate insulating film, even if the capacitance of an equivalent silicon oxide thickness is the same, the actual physical thickness can be increased by a factor of “dielectric constant of high dielectric film/dielectric constant of silicon oxide film”, and as a result, the gate-leakage current can be reduced. As a high dielectric material, oxides typified by hafnium-based oxides such as Hf—O, Hf—Si—O, Hf—Si—O—N, Hf—Al—O, and Hf—Al—O—N have been studied.
Incidentally, the inventor of the present invention has made a prior-art search based on the invented results, in the light of a first aspect of forming a gate insulating film made of a high dielectric material and a gate electrode made of a metal material and a second aspect of capping a high dielectric material forming a gate insulating film. As a result, Japanese Patent Application Laid-Open Publication No. 2006-080133 (Patent Document 1) has been extracted regarding the first aspect, and Japanese Patent Application Laid-Open Publication No. 2006-310801 (Patent Document 2) has been extracted regarding the second aspect.
The main subject of Japanese Patent Application Laid-Open Publication No. 2006-080133 (Patent Document 1) is to form a gate insulating film by using hafnium oxide which is a high dielectric material and form gate electrodes of an n channel MIS transistor and a p channel MIS transistor by using gate electrode materials suitable for the respective work functions as a whole, and metal materials are used therein for achieving the main subject. However, the Patent Document 1 does not describe the aspect of capping the high dielectric film forming the gate insulating film.
The main subject of Japanese Patent Application Laid-Open Publication No. 2006-310801 (Patent Document 2) is to solve a problem of trapping which occurs at an interface between a high dielectric film and a polysilicon film forming a gate electrode as a whole, and the gate insulating film is capped by an intermediate layer (so-called buffer layer) before forming the gate electrode for achieving the main subject.